1. Field
This disclosure relates generally to integrated circuit logic design and, more specifically, to techniques for performing conditional sequential equivalence checking of an integrated circuit logic design.
2. Related Art
In general, formal verification involves rigorously proving that an integrated circuit (IC) logic design (design) satisfies an associated specification. Typically, the specification of a verification problem includes a netlist representation of a design and a set of expected values for specified nets of the netlist. A ‘netlist’ comprises gates of various functions (which evaluate to Boolean values over time) and edges (which represent interconnections between the gates). A ‘trace’ may be a sequence of binary (i.e., ‘0’ or ‘1’) values to gates over time or a sequence of ternary values (i.e., ‘0’, ‘1’, or ‘X’, where value ‘X’ refers to an unknown value) to gates over time.
A gate may, for example, fall into one of four broad functional categories: constant gates, random gates, combinational gates, and state elements (e.g., registers and sequential gates, such as latches and flip-flops). A constant gate produces a logic level that does not vary with time. A random gate (also referred to as a primary input) may assume any logic level in any time-step independent of all other gates. A combinational gate is a logical element such as an AND gate, an OR gate, a NAND gate, a NOR gate, etc. A sequential gate has an associated initial value function and a next state function. The value of a sequential gate at time ‘0’ (t0) is the value of the initial value function. The value of a sequential gate at time ‘i+1’ is equal to the value of the next state function of the sequential gate at time ‘i’.
As an example, a verification problem may include determining whether a state exists in which a particular signal is asserted, where assertion of the particular signal indicates a fault. Using formal verification, an attempt is made to find a counter-example trace that includes a sequence of net values over time (states) that leads to an assertion of a particular signal or prove that no counter-example trace exists that leads to the assertion of the particular signal. Formal verification is often performed using state space search algorithms, which include unbounded and bounded exhaustive search algorithms. Bounded exhaustive search algorithms attempt to find an assertion of a particular signal that occurs within ‘N’ time-steps from an initial state of a design. Unbounded exhaustive search algorithms increase ‘N’ until no states are encountered that have not already been encountered for smaller values of ‘N’ (a condition referred to as a ‘fixed-point’). If no path from an initial state to a violating state (i.e., a state in which the particular signal is asserted) is encountered before the fixed-point is reached, then correctness of a design can be inferred.
The number of verification cycles required to perform an exhaustive state space search increases exponentially with the number of state elements (e.g., registers, latches, flip-flops, etc.). This exponential relationship makes formal verification impractical for designs containing a large number of state elements (e.g., one-hundred or more state elements). As a result, semi-formal verification has been employed as a verification technique for large designs. Semi-formal verification leverages formal algorithms by applying the formal algorithms to larger designs in a resource-bounded manner. While requiring less computation time (as compared to formal verification), semi-formal verification may only achieve partial verification coverage.